The application of high-quality electrically-insulating layers is required for numerous electronic and optoelectronic semiconductor-based devices. The formation of these insulating layers, typically oxide states of elements or compounds, can be accomplished by various means including deposition techniques such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, sputtering, electron beam or thermal evaporation, etc. or by oxidizing materials that have already been deposited or grown by the aforementioned methods.
In many semiconductor-based devices it is advantageous for the insulating layer to reside between single crystal semiconductor layers, such as in vertical-cavity surface-emitting lasers (VCSELs), see U.S. Pat. No. 6,238,944 to P. D. Floyd, entitled “Buried heterostructure vertical-cavity surface-emitting laser diodes using impurity induced layer disordering (IILD) via a buried impurity source;” and current aperture vertical electron transistors (CAVETs), see Y. Gao, I. Ben-Yaacov, U. K. Mishra, and E. L. Hu, “Optimization of AlGaN/GaN current aperture vertical electron transistor (CAVET) fabricated by photoelectrochemical wet etching,” Journal of Applied Physics 96, 6925 (2004), among others.
In the particular cases of VCSELs and CAVETs, the operation of the semiconductor-based device requires that the buried insulating layer not be laterally continuous, and that the non-insulating part of the layer be electrically conductive. This type of semiconductor device structure typically requires a material that can be grown epitaxially within the structure, that can be laterally oxidized in a manner that will not significantly oxidize other materials within the same device structure (known as “selective oxidation”), and will not react with neighboring materials during the selective oxidation step.
In the III-As material system, this nature of lateral oxidation of an epitaxial buried semiconductor layer is accomplished via an AlxGa1-xAs layer with high aluminum mole fraction x, see K. D. Choquette, K. M. Geib, C. I. H. Ashby, R. D. Twesten, O. Blum, H. Q. Hou, D. M. Follstaedt, B. E. Hammons, D. Mathes, and R. Hull, “Advances in selective wet oxidation of AlGaAs alloys,” IEEE Journal of Selected Topics in Quantum Electronics 3, 916 (1997), and has been widely exploited for the fabrication of III-As-based VCSELs. See U.S. Pat. No. 6,238,944, supra; see also M. DeVittorio, P. O. Vaccaro, M. DeGiorgi, S. DeRinaldis, and R. Cingolani, “Local degradation of selectively oxidized AlGaAs/AlAs distributed Bragg reflectors in lateral-injection vertical-cavity surface-emitting lasers,” Applied Physics Letters 77, 3905 (2000). In addition to buried insulator layers, insulating layers at the surface of a semiconductor device structure are typical, for instance as a gate dielectric or surface passivation layer in a transistor structure.
In Si-based transistors, a high quality insulator can be formed by oxidizing the surface of the Si; however, in many other semiconductor material systems, particularly compound semiconductors, direct oxidation of the semiconductor does not provide an oxide layer with adequate electrical properties.
Alternatively, in the case of an insulating layer at the surface, it may be advantageous to deposit an insulating material on the semiconductor device surface immediately after growing the semiconductor device layers to limit the amount of contamination and the formation of defects at the semiconductor/insulator interface. Materials compatibility issues may preclude the deposition of various semiconductors, insulators, and metals within the same growth chamber, and therefore, the in situ deposition of an insulator on the semiconductor may not be possible. In this case, a material must be deposited that is compatible with the semiconductor growth technique and can be selectively oxidized without reacting with the neighboring semiconductor material.
While the oxidation of Si for gate oxides in transistors and the lateral oxidation of buried AlxGa1-xAs layers for VCSELs is well established, the application of these techniques is more challenging for III-N (i.e., GaN, AlN, InN, and alloys thereof) and SiC wide bandgap semiconductors. These semiconductors are used in a variety of electronic and optoelectronic applications including high power electronics, high frequency transistors, light-emitting diodes, and lasers.
The ability to incorporate high quality insulating layers within these semiconductors and/or at the semiconductor device surface would increase current device performance and open up new avenues of device design. In the case of the III-Ns, direct oxidation of GaN requires a high temperature, typically greater than 800° C., and has an oxidation rate of only a few nanometers of oxide growth after 5 hours at 800° C. in a dry O2 environment, see S. D. Wolter, J. M. DeLucca, S. E. Mohney, R. S. Kern, and C. P. Kuo, “An investigation into the early stages of oxide growth on gallium nitride,” Thin Solid Films 371, 153 (2000) (“Wolter 2000”), and an oxidation rate of approximately 20 nm/hr at 900° C. in a dry air environment. See S. D. Wolter, S. E. Mohney, H. Venugopala, A. E. Wickenden, and D. D. Koleske, “Kinetic study of the oxidation of gallium nitride in dry air,” Journal of the Electrochemical Society 145, 629 (1998) (“Wolter 1998”). These oxidation conditions are not selective to other III-N materials or metals and the oxidation rate is insufficient for practical applications of lateral oxidation.
An alternative method of oxidizing GaN is via photo-enhanced wet oxidation, where ultraviolet (UV) light is used to induce the oxidation process in an aqueous phosphoric acid solution. See U.S. Pat. No. 6,190,508, to L.-H. Peng, Y.-C. Hsu, C.-Y. Chen, J.-K. Ho, and C.-N. Huang, entitled “Method of oxidizing nitride material enhanced by illumination with UV light at room temperature.” This process has many inherent disadvantages including additional processing steps such as depositing a metal electrode on the sample to act as a cathode, which must be etched away after the oxidation step. Additionally, since this process requires the GaN layer to be exposed to UV light, the GaN layer cannot be buried under a material with a smaller bandgap, which would absorb the UV light before it can reach the GaN layer, limiting device design.
Furthermore, the acidic environment required for the oxidation process may not be compatible with all desired materials.
A reported method for the selective lateral oxidation of III-N materials is through the anodic oxidation of a buried In0.18Al0.82N layer, which is lattice-matched to GaN, see J. Dorsaz, H.-J. Buhlmann, J.-F. Carlin, N. Grandjean, and M. Ilegems, “Selective oxidation of AlInN layers for current confinement in III-Nitride devices,” Applied Physics Letters 87, 072102 (2005), in a nitrilotriacetic acid solution. While the In0.18Al0.82N layer has been shown to be selectively laterally oxidized for many micrometers over GaN and InGaN layers, the process requires a metal electrode to be deposited on the sample, which creates additional processing steps. Moreover, the In0.18Al0.82N has a high electrical resistivity, which is not desirable for many applications.
An alternative method is the lateral oxidation of buried conductive n-type GaN layers in a III-N device structure consisting of p-type GaN, unintentionally-doped GaN, and InGaN. See C.-F. Lin, W.-C. Lee, B.-C. Shieh, D. Chen, D. Wang, and J. Han, “Fabrication of current confinement aperture structure by transforming a conductive GaN:Si epitaxial layer into an insulating GaOx layer,” ACS Applied Materials and Interfaces 6, 22235 (2014). This method first requires a wet electrochemical etching step in oxalic acid solution to modify the n-type GaN layer into a nanoporous GaN structure. This is followed by the oxidation of the newly formed nanoporous GaN layer via photoelectrochemical oxidation in deionized water. Similar to the previously discussed methods, this process requires further processing steps, such as the deposition of a metal electrode on the sample for the wet etching and oxidation steps, material incompatibility issues with the wet etch environment, and limitation in device design as any other n-type GaN layer in the structure would also be etched and oxidized as well.